1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a plasma display panel having different dielectrics formed on a front substrate so as to improve its light emission efficiency and lower its driving voltage.
2. Description of the Related Art
In general, a plasma display panel (hereafter, referred to as PDP) is a display device using the visible rays generated when vacuum ultraviolet rays generated by gas discharge excite phosphor.
The PDP is thinner in thickness and lighter in weight than the cathode ray tubes (CRTs) that have been usually employed as display devices. The PDP has an advantage in that a high definition and large-sized screen can be realized.
The PDP that has such advantages described above includes many discharge cells arranged in matrix fashion and each of the discharge cells works as one pixel of a screen.
FIGS. 1 and 2 illustrate the structure of three-electrode AC surface discharge type PDP in the related art respectively. Specifically, FIG. 2 is a drawing in which a front substrate is turned by 90xc2x0 to a rear substrate to describe a whole schematic structure of the discharge cells. Even though FIGS. 1 and 2 depict one discharge cell 1 for the convenience of explanation, a PDP has generally many millions of the discharge cells 1 shown in the FIGS. 1 and 2 arranged in matrix fashion.
Referring to FIGS. 1 and 2, a three-electrode AC surface discharge type PDP in the related art includes first electrodes 12Y and second electrodes 12Z formed on a front substrate 10 and address electrodes 20X formed on a rear substrate 18.
A front dielectric layer 14 and a protective layer 16 are laminated on the front substrate 10 that has the first electrodes 12Y and the second electrodes 12Z arranged in parallel. Wall charge generated during plasma discharge is stored on the front dielectric layer 14. The front dielectric layer 14 is designed to have a thickness within 30 xcexcm to 45 xcexcm. The protective layer 16 protects the front dielectric layer 14 from damages caused by sputtering during plasma discharge and also improves the second electrons emission efficiency. The protective layer 16 is usually made of magnesium oxide (MgO).
A rear dielectric layer 22 and barrier ribs 24 are formed on the rear substrate 18 that has the address electrodes 20X formed thereon. A phosphor layer 26 is coated on the surfaces of the rear dielectric layer 22 and the barrier ribs 24. The address electrodes 20X is formed in the direction to cross over the first electrodes 12Y and the second electrodes 12Z. The barrier ribs 24 are formed in parallel with the address electrodes 20X so as to prevent the ultraviolet rays and the visible rays generated by the plasma discharge from leaking into the neighboring discharge cells 1.
The phosphor layer 26 is excited by the ultraviolet rays generated during the plasma discharge so as to generate one of visible rays of red, green and blue colors. The inert gas for discharge is injected into discharge spaces prepared between the front substrate 10/the rear substrate 18 and the barrier ribs 24. A black matrix not shown in the FIGS. 1 and 2 is formed between the first electrode 12Y and the second electrode 12Z which are respectively formed in the neighboring discharge cells 1.
In this AC surface discharge type PDP, one frame is divided into a few subfields each of which is different from others in the number of discharge times so as to display the gray levels of images. Each of the subfields is divided into a reset period for generating a uniform discharge, an address period for selecting a discharge cell, and a sustain period for displaying gray levels according to the number of discharge times. For example, to display an image in 256 gray levels, the frame period (16.67 ms) corresponding to one 60th second is divided into eight subfields.
Each of the eight subfields is divided into the reset period, the address period and a sustain period. The reset period of each subfield is the same as the address period in length while the sustain period increases at each subfield at the ratio of 2n(n=0, 1, 2, 3, 4, 5, 6 and 7). In this way, the sustain period of each field is different from that of other fields, and hence the gray levels of the image can be displayed.
In the reset period, reset pulses are applied to the first electrodes 12Y to cause reset discharge. In the address period, scan pulses are applied to the first electrodes 12Y and data pulses are applied to the address electrodes 20X to cause address discharge between two electrodes 12Y and 20X. The wall charge is created on the front dielectric layer 14 and the rear dielectric layer 22 during the address discharge. In the sustain period, AC signals that are alternatively applied to the first electrodes 12Y and the second electrodes 12Z cause sustain discharge between two electrodes 12Y and 12Z.
Such a PDP in the related art varies in its light emission efficiency and its driving voltage according to the thickness of the front dielectric layer 14. For example, when the front dielectric layer 14 is formed to be thicker than a predetermined thickness, the discharge current that is applied to the PDP during the sustain period allows the wall charge to be generated uniformly on the entire areas of the first electrodes 12Y and the second electrodes 12Z and hence the wall charge enhance the brightness very greatly. However, if the front dielectric layer 14 is formed to be thicker than a predetermined thickness, the thick front dielectric layer 14 may allow a high voltage to be applied in order to cause address discharge between the first electrodes 12Y and address electrodes 20X during address period.
On the other hand, when the front dielectric layer 14 is formed to be thinner than a predetermined thickness, the discharge current that is applied to the PDP during the sustain period results in the wall charge""s concentration on the inner edge portions of the first electrodes 12Y and the second electrodes 12Z. This is not expected to enhance the brightness. However, if the front dielectric layer 14 is farmed to be thinner than a predetermined thickness, the thin front dielectric layer 14 may allow a low voltage to be applied in order to cause address discharge between the first electrodes 12Y and address electrodes 20X during address period.
Thus, in the PDP of the related art, if the front dielectric layer 14 is formed to be thick, the higher driving voltage is required to cause address discharge. In contrast, if the front dielectric layer 14 is formed to be thin in order to lower the driving voltage required to cause the address discharge, the discharge efficiency degenerates. Therefore, in the PDP of the related art, it is impossible to enhance the light emission efficiency and lower the driving voltage at the same time.
An object of invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Accordingly, it is an object of the present invention to enhance the light emission efficiency and lower the driving voltage at the same time in PDP.
These and other objects and advantages of the invention are achieved by providing a plasma display panel which includes: a plurality of first electrodes formed on a front substrate, for receiving scan pulses during address period; a plurality of second electrodes formed near to each of the first electrodes, for receiving first sustain pulses during sustain period; a plurality of third electrodes formed spaced widely from each of the second electrodes, for receiving second sustain pulses during sustain period; a dielectric layer having a first dielectric sub-layer and a second dielectric sub-layer, the first dielectric sub-layer being formed on a backside of the first electrodes, the second dielectric sub-layer being formed on backsides of the second electrodes and the third electrodes, the first dielectric sub-layer being different from the second dielectric sub-layer in thickness; a plurality of address electrodes formed on a rear substrate in a direction to cross over the first electrodes, the second electrodes and the third electrodes; and a plurality of barrier ribs formed between the neighboring address electrodes and parallel with the address electrodes.
It is desired that the first dielectric sub-layer is thinner than the second dielectric sub-layer.
It is desired that the first dielectric sub-layer is arranged in a stripe shape and parallel with the first electrodes.
It is desired that the second dielectric sub-layer is arranged in a stripe shape and parallel with the second electrodes and third electrodes.
It is desired that the dielectric layer gets gradually thicker with a predetermined slope at a boundary area between the first sub-dielectric layer and the second sub-dielectric layer as it goes from the first dielectric sub-layer to the second dielectric sub-layer.
It is desired that the dielectric layer gets abruptly thicker with a stiff step at a boundary area between the first sub-dielectric layer and the second sub-dielectric layer as it goes from the first dielectric sub-layer to the second dielectric sub-layer.
According to another aspect of the invention, a plasma display panel includes: a plurality of first electrodes formed on a front substrate, for receiving scan pulses during address period; a plurality of second electrodes formed near to each of the first electrodes, for receiving first sustain pulses during sustain period; a plurality of third electrodes formed spaced widely from each of the second electrodes, for receiving second sustain pulses during sustain period; a dielectric layer having a first dielectric sub-layer and a second dielectric sub-layer, the first dielectric sub-layer being formed on a backside of the first electrodes, the second dielectric sub-layer being formed on backsides of the second electrodes and the third electrodes, the dielectric layer getting gradually thicker with a predetermined slope at a boundary area between the first sub-dielectric layer and the second sub-dielectric layer as it goes from the first dielectric sub-layer to the second dielectric sub-layer; a plurality of address electrodes formed on a rear substrate in a direction to cross over the first electrodes, the second electrodes and the third electrodes; and a plurality of barrier ribs formed between the neighboring address electrodes and parallel with the address electrodes.
According to further another aspect of the invention, a plasma display panel includes: a plurality of first electrodes formed on a front substrate, for receiving scan pulses during address period; a plurality of second electrodes formed near to each of the first electrodes, for receiving first sustain pulses during sustain period; a plurality of third electrodes formed spaced widely from each of the second electrodes, for receiving second sustain pulses during sustain period; a dielectric layer having first dielectric sub-layer and second dielectric sub-layer, the first dielectric sub-layer being formed on a backside of the first electrodes, the second dielectric sub-layer being formed on backsides of the second electrodes and the third electrodes, the dielectric layer getting abruptly thicker with a stiff step at a boundary area between the first sub-dielectric layer and the second sub-dielectric layer as it goes from the first dielectric sub-layer to the second dielectric sub-layer in their boundary areas, the first dielectric sub-layer being thinner than the second dielectric sub-layer; a plurality of address electrodes formed on a rear substrate in a direction to cross over the first electrodes, the second electrodes and the third electrodes; and a plurality of barrier ribs formed between the neighboring address electrodes and parallel with the address electrodes.
It is desired that the first dielectric sub-layer and the second dielectric sub-layer are formed only in discharge between the neighboring barrier ribs.
According to still another aspect of the invention, a plasma display panel includes: a plurality of first electrodes formed on a front substrate, for receiving scan pulses during address period; a plurality of second electrodes formed near to each of the first electrodes, for receiving first sustain pulses during sustain period; a plurality of third electrodes formed spaced widely from each of the second electrodes, for receiving second sustain pulses during sustain period; a dielectric layer having first dielectric sub-layer and second dielectric sub-layer, the first dielectric sub-layer being formed on a backside of the first electrodes, the second dielectric sub-layer being formed on backsides of the second electrodes and the third electrodes, the first dielectric sub-layer being thinner than the second dielectric sub-layer, the first dielectric sub-layer and the second dielectric sub-layer being formed only in discharge cells between the neighboring barrier ribs; a plurality of address electrodes formed on a rear substrate in a direction to cross over the first electrodes the second electrodes and the third electrodes; and a plurality of barrier ribs formed between the neighboring address electrodes and parallel with the address electrodes.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.